1. Field of the Invention
The present invention relates to a semiconductor device with anti-fuse elements.
2. Description of the Related Art
When a faulty memory cell which fails to operate normally is found in a semiconductor device such as a DRAM (Dynamic Random Access Memory) or the like, the faulty memory cell is replaced with a backup memory cell, and the address of the faulty memory cell is stored. If there is a request to access the stored address of the faulty memory cell, then the backup memory cell that has replaced the faulty memory cell is accessed.
The address of the faulty memory cell is stored by anti-fuse elements.
An anti-fuse element has an insulating film. When a high voltage is applied to the insulating film, the insulating film causes a dielectric breakdown to change the anti-fuse element from an insulated state to a conductive (connected) state, thereby writing data therein. One example of an anti-fuse element is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), which writes data when its gate insulating film breaks down.
Patent document 1 (JP No. 2000-132992A) discloses a semiconductor device having a plurality of anti-fuse elements disposed parallel to each other in combination with corresponding selective MOSFETs.
Patent document 2 (JP No. 2008-269711A) discloses a semiconductor device which operates in synchronism with a clock signal to write data into anti-fuse element when the clock signal is a high level signal and verify whether the anti-fuse element is rendered conductive or not when the clock signal is a low level signal.
The semiconductor devices disclosed in Patent documents 1, 2 break down the insulating film, i.e., write data into the anti-fuse elements, by applying a voltage of constant level to the anti-fuse elements. The inventor of the present invention has found that the disclosed semiconductor devices have problems that will be described below.
The voltage at which the insulating film of an individual anti-fuse element breaks down tends to vary due to fabrication process variations. Therefore, a plurality of anti-fuse elements are liable to have various voltages for breaking down the insulating films thereof, i.e., various write voltages.
It is assumed that a voltage of constant level is applied to a plurality of anti-fuse elements having different write voltages to write data into the anti-fuse elements. If the write voltages vary in an increasing direction, then data may not be correctly written into the anti-fuse elements because the applied voltage is not sufficient. On the other hand, if the write voltages vary in a decreasing direction, anti-fuse elements adjacent to the anti-fuse elements into which data are to be written may be erroneously connected because the applied voltage is excessively high.
FIG. 1 of the accompanying drawings is a diagram illustrative of the problems posed when the applied voltage is excessively high.
Potential AF_G1=VPPSVT is applied via a power line to the gate of an anti-fuse element (MOSFET) into which data are to be written, and potential VBBSVT is applied via a power line to the source, drain, and N++ region of the anti-fuse element (MOSFET).
Potential AF_G2=VSS (ground potential) is applied via a power line to the gate of an adjacent anti-fuse element, and potential VBBSVT is applied via the power line to the source, drain, and N++ region of the adjacent anti-fuse element.
If an excessively high voltage is applied to the anti-fuse element into which data are to be written, a short circuit will occur between the power line connected to the gate of the anti-fuse element into which data are to be written and the power lines connected to the gate and N++ region of the adjacent anti-fuse element, through the substrate, tending to cause the adjacent anti-fuse element to be connected erroneously.